In telecommunication applications where clock and data signals are respectively transmitted or received through separate cables, a phase difference between the clock and data signals often becomes more prominent during propagation over long distances. This is undesirable for many telecommunication applications that use synchronized digital systems, which require the clock and data signals to be in-phase for proper operations.
A single cable carrying only one data signal is therefore used in placed of the dual separated cables carrying the clock and data signal to avoid development of the phase difference between the clock and data signals. A data signal is transmitted and received in a non-return to zero (NRZ) format in which a clock signal is recovered from the data signal. The data signal transmitted and received in this manner is commonly known as an NRZ data signal.
A clock and data recovery (CDR) circuit is commonly used for recovering the clock signal from the NRZ data signal and is an important component in many telecommunication systems, such as high-speed optoelectronic data transceivers. The CDR circuit typically consists of a clock recovery block for recovering the clock signal from the NRZ data signal and a re-timing block for re-timing the NRZ data signal.
Most CDR circuits work in conjunction with phase-locked loops to provide the in-phase clock and data signals required by the synchronized digital systems. These CDR circuits have phase detectors, such as Alexander and Hogge phase detectors, that are used for comparing phases of frequency signals and providing control signals to other parts of the CDR circuit. However, such phase detectors significantly limit the working frequency range of input signals to the CDR circuits. This limitation to the working frequency range of input signals is substantially avoided through the use of a frequency detector in addition to the phase detector. The frequency detector and the phase detector collectively increase the working frequency range of input signals to the CDR circuits.
A CDR circuit 100 based on a quadricorrelator approach is disclosed in “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s”, by Pottbäcker et al., IEEE Journal of Solid-State Circuits, vol.SC-27, pp.1747-1751, December 1992 and shown in FIG. 1. The quadricorrelator based CDR circuit 100 requires quadrature signals generated from an off-chip voltage-controlled oscillator (VCO) 102 to be fed to a phase detector (PD) 104 and quadrature phase (QP) detector 106 for proper operation.
The VCO 102 provides a VCO signal with a clock frequency and a VCO delayed signal, wherein both signals are sampled by the NRZ data signal at every transition. This creates transition pulses at outputs Q1 and Q2 of the PD 104 and QP detector 106 respectively whenever the current operating frequency of the VCO 102 and the data bit rate of the NRZ data signal is different. FIGS. 2a and 2b illustrate respectively output waveforms generated by Q1 of the PD 102 and Q2 of the QP detector 106 when the clock frequency (fVCO) is greater than frequency of the data bit rate (fb) and when fVCO is less than fb respectively.
The PD 104 generates an output signal which is fed to a frequency detector (FD) 108 for sampling an output signal received by the FD 108 from the QP detector 106. The PD 104, QP detector 106 and FD 108 form an on-chip component 110 of the quadricorrelator based CDR circuit 100. A frequency difference signal is generated at an output Q3 of the FD 108.
FIGS. 3a and 3b show timing diagrams of output waveforms from Q1, Q2 and Q3 of the PD 104, QP detector 106 and FD 108 respectively when fVCO is greater than fb and when fVCO is less than fb respectively. A summed output of Q1 and Q3 when fVCO is greater than fb and when fVCO is less than fb are respectively depicted in FIGS. 3a and 3b. If the output waveform from Q2 is in a negative state during a rising edge of the output waveform from Q1, the output waveform of Q3 will be in a negative state. If the output waveform from Q2 is in the negative state during a falling edge of the output waveform from Q1, the output waveform from Q3 will be in a positive state. If the output waveform from Q2 is in the positive state, the output waveform from Q3 will be in a zero state during the falling and rising edge of the output waveform from Q1. Therefore, when the sum of the output waveforms from Q1 and Q3 is fed to the VCO 102 via a loop filter, the VCO 102 will be in a locked state.
In the quadricorrelator based CDR circuit 100, an off-chip delay line 112 is coupled to the off-chip VCO 102 for the purpose of generating quadrature signals. However, the externally generated quadrature signals render the quadricorrelator based CDR circuit 100 unsuitable for monolithic implementation.
One method of generating on-chip quadrature signals for monolithic implementation is to use an on-chip VCO that is capable of oscillating at twice the frequency of the desired clock frequency. An on-chip frequency divider, such as a master-slave D-flip flop is then coupled to the on-chip VCO to facilitate on-chip quadrature signal generation. However, this method requires high power consumption. Furthermore, any asymmetry in the duty cycle at the input of the master-slave D-flip flop, or any mismatch in the input circuitry of the master-slave D-flip flop can degrade the accuracy of generating the quadrature signals. Solving these problems will further increase the circuit complexity and power consumption.
Another method of generating the on-chip quadrature signals is to couple two identical on-chip VCOs together in such a way as to force the respective outputs of the VCOs to be 90° out of phase. However, this method requires considerably larger chip area to contain the two on-chip VCOs and also higher power consumption.
Still another method of generating the on-chip quadrature signals is to use a ring oscillator. However, the ring oscillators generally have poor noise performance and are therefore unsuitable for high-performance applications.
There is, therefore, a need for a CDR circuit based on a quadricorrelator approach in which on-chip quadrature signals are generated with low power consumption and small die area requirement.